An analog-to-digital (AD) converter is one of key digital circuit devices for converting an analog signal into a corresponding digital signal. Some AD conversion techniques are proposed and put into practical use as ones suitable for converting a relatively low frequency analog signal such as an audio signal into a, for example 10 bits or higher bit (or high resolution) digital signal. Typical AD conversion techniques include a sequential comparison type AD converter and a cyclic AD converter.
FIG. 5 is a block diagram illustrating a basic construction of a typical sequential comparison type AD converter. The m-bits sequential comparison type AD converter 30 comprises a sample/hold circuit 31, a comparator 32, a control logic 33 and a digital-to-analog converter (referred to as a DAC below) 34. An analog input signal to be digitized is inputted to the sample/hold circuit 31. An output from the sample/hold circuit 31 is inputted to the inverting (or −) input terminal of the comparator 32 by way of a resistor 35 and a reference value (for example, a ground potential) is inputted to the non-inverting (or +) input terminal of the comparator 32. An output signal from the comparator 32 is inputted to the control logic 33 to be converted into an m-bits digital output signal that is also inputted to the m-bits DAC 34. An analog signal outputted from the DAC 34 is inputted (or fed back) to the inverting input terminal of the comparator 32.
Now, briefly describing the operation of the sequential comparison type AD converter 30 as shown in FIG. 5, the sample/hold circuit 31 samples and holds instantaneous values of the analog input signal under control of the sample/hold signal that is supplied thereto. The analog signal that is sampled and held by the sample/hold circuit 31 is inputted to the comparator 32 to which an analog voltage corresponding to the most significant bit (MSB, or the mth bit in this particular example) from the control logic 33 is firstly applied, thereby obtaining a difference signal between the output from the DAC 34 and the sampled analog voltage from the sample/hold circuit 31. The comparator 32 makes a judgment whether the difference signal is positive or negative. The control logic 33 operates based on a clock signal applied thereto and determines “1” or “0” as the output for the mth bit depending on positive or negative output of the comparator 32. Thereafter, similar operations are sequentially repeated to make a judgment of “1” or “0” for the (m−1)th bit, . . . , the 2nd bit and finally the least significant bit (i.e., LSB or the IST bit). Upon completing judgments for all bits from the MSB to the LSB, the control logic 33 outputs the digitized (or AD converted digital) value before the sample/hold circuit 31 acquires subsequent samples of the analog input signal at subsequent instances. Repetition of the aforementioned AD conversion operation results in AD conversion of the sequentially inputted analog signal. In such sequential comparison type AD converter 30, the DAC 34 is essential and such DAC 34 generally employs R-2R ladder circuits (i.e., current distribution type ladder circuits) or C-2C charge distribution type ladder circuits. However, such ladder circuits must be extremely precise and occupy a very large area on a substrate when implementing in a semiconductor integrated circuit (IC), thereby making it very difficult to implement in an IC or miniaturize.
A cyclic AD converter is proposed in order to overcome such disadvantages and is disclosed in some publications including the following non-patent document: Chen-Chung Shin, et. al., “Reference Refreshing Cyclic Analog-to-Digital and Digital-to-Analog Converters”, IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 4, August 1986, pp 544-554.
FIG. 6 is a block diagram illustrating a basic construction of a conventional cyclic AD converter 40. The cyclic AD converter 40 comprises a sample/hold circuit 41, a comparator 42, a control logic 43, a reference value switching circuit 44, an adder 45, an X2 amplifier (i.e., amplifier having the amplification factor of 2) 46 and an input switch 47. The cyclic AD converter 40 is essentially replacing the DAC 34 of the sequential comparison type AD converter 30 as illustrated in FIG. 5 by the X2 amplifier 46 and the reference value switching circuit 44.
In the cyclic AD converter 40, an analog signal to be digitized is inputted to the sample/hold circuit 41 by way of the switch 47 that operates under control of a sample/hold signal. An output from the sample/hold circuit 41 is inputted to the inverting input terminal of the comparator 42 having the non-inverting input terminal to which a threshold value (a reference value) is applied and also to the non-inverting input terminal of the adder 45. A comparison output from the comparator 42 is inputted to the control logic 43 that operates under control of a clock. The control logic 43 outputs a digitized output and a control signal for controlling the reference value switching circuit 44. An output form the reference switching circuit 44 is inputted to the inverting input terminal of the adder 45. And an output signal from the adder 45 is amplified by the factor of 2 by the X2 amplifier 46 and inputted to the sample/hold circuit 41 by way of the switch 47.
Now, the operation of the cyclic AD converter 40 will be briefly described hereunder. Firstly, the switch 47 is controlled to apply an analog input signal to the sample/hold circuit 41 that is designed to sample/hold instantaneous values (samples) of the analog input signal. The comparator 42 compares each sample with the threshold value and a comparison result that is either “H (or high level)” or “L (or low level)” is inputted to the control logic 43. It is to be noted here that the control logic 43 controls the switch in the reference value switching circuit 44 so that a reference value Vref or a ground potential is inputted to the adder 45 when the comparison result of the comparator 42 is H or L, respectively. Also, the control logic 43 sets the mth bit (or the MSB) to “1” or “0” when the comparison result of the comparator 42 is H or L, respectively. Then, an output from the adder 45 representing a difference signal of the sample value from the sample/hold circuit 41 and the reference voltage or ground potential that depends on the comparison result of the comparator 42 is amplified by the factor of 2 by the X2 amplifier 46 before being inputted to the sample/hold circuit 41 by way of the switch 47. Similarly, the above operation to make a judgment of the digital value “1” or “0” for the (m−1)th and the subsequent bits will be repeated until the digital value for the LSB is determined and outputted from the control logic 43.
As apparent from the above description, since the cyclic AD converter 40 as described hereinabove requires no DAC unlike the sequential comparison type AD converter 30, no large circuit area is required for implementing the circuit in, for example, an IC and thus enabling to miniaturize the circuit. However, since the adder 45 and the X2 amplifier 46 are generally implemented using active devices, there is a drawback to consume relatively large power as compared to non-active (i.e., passive) devices. In particular, low power consumption is essential to portable audio equipment, hearing aids and the like that are driven by a built-in battery because an operation time by a fully charged battery is one of key factors of such electronic appliances. In other words, reducing power consumption of an AD converter is a very important technical feature to enhance competitiveness of such electronic appliances in the marketplace.